AMD Ryzen 8000 “Zen 5” Specs and Release Date

We know a fair bit about AMD’s next-gen Ryzen 8000 processors by now. This includes the core architecture, process technology, cache structures, and thread counts. The late September leak from Moore’s Law is Dead gave us a first look at the finer details of the Zen 5 core and its capabilities. Codenamed “Nirvana”, the fifth iteration of the Zen architecture will focus on single-threaded performance, significantly improving the gaming performance of the Ryzen 8000 CPUs.

The Zen 5 core has been upgraded on all fronts, including the frontend, backend, memory sub-system, and cache. The L1I data cache, an input cache that sits next to the decoder and branch predictor, has been increased from 32KB to 48KB 12-way. Similarly, the Data Translation Buffer (DTLB) and the PWC have also been expanded for faster address translation.

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In any out-of-order CPU, the branch predictor is one of the most crucial components. It directly affects the utilization of the various ALUs by dictating the flow of the pipeline. It affects stalls and flushes (in the case of incorrect branches) that are highly detrimental to IPC. Zen 5’s branch predictor is capable of “Zero bubble” conditional branches.

This means that the branch predictor of Zen 5 can access the BTB without any penalties (mostly one RR) or bubbles. The Branch Target Buffer, Zen 5 also upgrades its capacity and accuracy, which is crucial in conditional indirect branches.

Interestingly, the decoder looks untouched, but the dispatch queue has been widened from 6 to 8 micro-ops with support for op fusion. This allows two micro-ops from the same instruction to be treated as one at certain points in the pipeline, doubling the effective throughput.

Coming to the backend, Zen 5 strengthens AMD’s already formidable Integer Execution. The ALU count has been increased from 4 to 6, paired with a larger Integer Scheduler. On the Vector/FP Side, 512-bit wide FP units have been added to improve AVX512 performance. The wider ALU may be limited to the Epyc offerings, leaving it fused on the Ryzen 8000 CPUs. The Memory Sub-system hasn’t been ignored either. Zen 5 can do 4 loads or 2 stores per cycle, up from 3 loads on Zen 4.

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From earlier leaks, we know that AMD’s Ryzen 8000 processors will use an upgraded core interconnect known as Ladder L3 Fabric (originally leaked by AdoredTV). This is related to the 3rd Gen Infinity Fabric, which will act as the die interconnects for AMD’s next generation of chiplet products.

The core counts and higher-level cache buffers are expected to remain unchanged. The Ryzen 8000 CPUs should feature up to 16 cores across two CCDs, each with 32MB of L3 cache. The L2 cache will remain 1MB per core or 16MB for the entire CPU. The core clocks should be on par or higher than the Ryzen 7000 parts. After all, the 4nm (N4) node is a customized variant of the 5nm process powering Zen 4.

The Ryzen 8000 CPUs are expected to land in mid to late 2024. You can expect a summer or fall launch.


Computer hardware enthusiast, PC gamer, and almost an engineer. Former co-founder of Techquila (2017-2019), a fairly successful tech outlet. Been working on Hardware Times since 2019, an outlet dedicated to computer hardware and its applications.
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