AMD’s next-gen Zen 5 core architecture is slated to land in mid to late 2024, with a reworked frontend, wider instruction issue, larger cache, and improved latencies. Powering the Ryzen 8000 processors and the Epyc Turin lineup, it’ll be a major overhaul of the Zen core architecture introduced back in 2017. The latest bit of info comes from Jim (AdoredTV), according to whom Zen 5 will introduce a new (on-die) core-to-core interconnect called Ladder L3 Fabric.
Zen 1 and 2 leveraged a crossbar (every core connected to every other) for the four cores on a CCX, while the Zen 3 and Zen 4 cores on a CCD are connected using a bi-directional ring bus.
Zen 5 will feature a unique core interconnect called Ladder L3 Fabric. In this layout, each core is directly connected to the opposite one. The adjacent cores are connected using a ladder-like common bus, which in turn is connected to the opposite bus via seven high-speed links. This topology should improve inter-core latency, gaming performance, etc.
In addition to an improved L3 cache topology, Zen 5 will also double or perhaps triple the L2 cache per core to 2MB or 3MB. This should improve the IPC by a low single-digit percentage, especially in multi-threaded workloads.
