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AMD Ryzen 5000 Mobile “Cezanne” Architectural Changes

We’re finally ready to share the architectural changes with the Ryzen 5000 mobile processors, codenamed Cezanne. From a higher level, the Renoir and Cezanne SoCs look identical. The core changes come in the form of a new core architecture (Zen 3), improvements to battery life, and an even faster Vega core.

Like Vermeer, the eight cores on a die share a unified L3 cache, albeit a smaller sized one. You can read more about the changes to the Zen 3 core here.

In terms of performance, AMD claims a 23% increase increase in multi-threaded performance which falls in line with what we saw with the desktop Zen 3 parts. This is, however, a comparison of the Ryzen 9 5980HX with the Ryzen 9 4900H.

On the multi-threaded side, AMD promises a gain of a rather sizable 108%, but if you look closely this is in comparison to Intel’s quad-core i7-1185G7. Not really surprising. Now for the battery life, the Ryzen 7 5800U is supposed to offer two extra hours compared to its predecessor, the 4800U.

It looks like the rumors were true and Cezanne was taped out just months after the launch of Renoir. Furthermore, the two APU families share the same pinout, allowing OEMs to use the same boards for both families.

Note: It looks like the power and efficiency-level have been implemented on the Lucienne (Ryzen 5000 using the Zen 2 core) chips as well via firmware updates.

The other core changes with Cezanne other than the new core are with respect to the memory controller and battery life optimization. Cezanne supports an upgraded memory controller, allowing an entry into low activity phase when idle to drastically reduce the power draw, plus a quick exit from the state as well. The memory PHY has been bypassed (something that controls signals, timing, and programmable parameters required to transfer control information and data to and from the DRAM devices), leveraging the SMU (System Management Unit) instead.

Cezanne features the same 7nm Vega core as Renoir, with up to 8 CUs or 512 shaders, however, the maximum boost clock has been yet again increased to 2.1GHz, along with improvements to the power efficiency and an overall increased TDP.

When it comes to power optimization Cezanne introduces two key improvements, namely per core on-chip power regulation and
Collaborative Processor Performance Control (CPPC), a part of the ACPI protocol. The former allows the scheduler to choose the fastest core for single-threaded workloads, improving latency and responsiveness, while also significantly increasing the bursts to higher power states faster. Overall, it replaces the traditional P-states with more fine-grained control over the power-performance ratio depending on the load and set profile.

PCOCPR allows setting individual voltages for each core depending on the load and the number of physical cores in use. As you can see in the above image, with Renoir, all the cores ran at the same voltage regardless of the load and the resultant frequency, resulting in unnecessary power consumption. Cezanne optimizes this allowing each core to run at a separate voltage depending upon the kind of load and resulting frequency. There’s also room for OS-based optimizations (QoS hooks) that let the core select the optimal frequency for each task.

Overall, these optimizations have increased the power efficiency of the Cezanne parts by as much as 26% when under load and nearly 50% when idle.

The standby time has increased by a massive 20 hours while the video playback and other lightly threaded workloads will last 1-2 hours longer on battery. You can read more about the performance and specifications of the Cezanne (Ryzen 5000) product stack here.

Areej

Computer Engineering dropout (3 years), writer, journalist, and amateur poet. I started my first technology blog, Techquila while in college to address my hardware passion. Although largely successful, it was a classic example of too many people trying out multiple different things but getting nothing done. Left in late 2019 and been working on Hardware Times ever since.

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