Some more data pertaining to AMD’s upcoming Ryzen 4000 “Vermeer” CPUs has surfaced. While most of it basically confirms what we already knew, there’s one surprise: The 4th Gen Ryzen CPUs will support up to 1TB of ECC DRAM (512GB per channel). As already reported earlier, we’ll get an updated CCD design with the new eight-core CCXs sharing 32 MB of L3 cache. Previously, with Matisse and Vermeer, the L3 cache was shared between the four cores in a CCX. This update will improve hit rates by allowing each core access to more level 3 cache memory.
The core counts are going to stay unchanged with the Vermeer flagship featuring up to 16 cores and 32 threads across two CCX/CCDs, along with 64 MB of total L3 cache. The primary performance boost will come from the increased IPC and higher clock speeds. AMD won’t be adopting AVX512 anytime soon, so the execution units should stay largely the same. The branch predictor may get an upgrade, along with the load-store units which are lagging behind Sunny Cove. Considering that there’s no node shrink this time around, the retire and reorder buffers will stay the same. Other than that, the registers might get tweaked along with the low-level caches.
- Intel Sunny Cove vs Zen 2 Core Architectures: Comparing Comet Lake, Ice Lake, and Ryzen 3000
- Intel vs AMD CPU Comparison: Difference Between the Two Architectures Explained
As for the increased clock speeds, we already know that engineering samples are able to hit 4.9GHz. Therefore, the retail chips should be able to feature a boost clock of at least 5GHz for the Ryzen 7 and Ryzen 9 models. I expect some improvements to the memory controller and the Infinity Fabric as well, similar to what we saw with Renoir.
The Ryzen 4000 desktop CPUs should be able to run much faster DDR4 memory, with improved Infinity Fabric and DRAM linking, resulting in lower latency and thereby, better gaming performance.
Finally, here’s the data from the leaked files about the PCH and I/O features of the new processors:
Scalable Data Fabric (IF): Connects the compute complexes, the I/O die, and the memory interfaces to each other.
- Handles request, response, and data traffic
- Handles probe traffic to facilitate coherency, supporting up to 512GB per DRAM channel
- Handles interrupt request routing (APIC)
- Scalable Control Fabric. This provides the data path that provides a configuration access path to all blocks
- Handles configuration request, response, and data traffic
- GMI2: Up to two special Data Fabric ports, for connections to the CCDs.
Memory interface
- 2 Unified Memory Controllers (UMC), each supporting one DRAM channel
- 2 DDR4 PHYs. Each PHY supports:
- 64-bit data plus ECC
- 1 DRAM channel per PHY
- 2 DIMMs per channel
- DDR4 transfer rates from 1333MT/s to 3200MT/s
- UDIMM support
PSP and SMU
- MP0 (PSP) and MP1 (SMU) microcontrollers
- This document refers to the AMD Secure Processor technology as Platform Security Processor (PSP).
- Thermal monitoring
- Fuses
- Clock control
NBIO
- PCI Device ID information uses Vendor ID is 1022h for all devices (see Table 18 [PCI Device ID
Assignments.]. - 2 SYSHUBs
- 1 IOHUB with IOMMU v2.x
- Two 8×16 PCIe controllers supporting Gen1/Gen2/Gen3/Gen4. Note that SATA Express is supported by combining an x2 PCIe® port and two SATA ports on the same 2 lanes.
- 24 total lanes combo PHY, UPI muxing
Fusion Controller Hub (FCH or southbridge (SB))
- ACPI
- CLKGEN/CGPLL for refclk generation
- GPIOs (varying number depending on muxing)
- LPC
- Real-Time Clock (RTC)
- SMBus
- SPI/eSPI
- Azalia
- High Definition Audio
- Up to 2 lanes of SATA Gen1/Gen2/Gen3, also provides the legacy SATA support for SATAe
- ports. Shared with PCIe
- SGPIO
- USB3.1 Gen2
- 4 ports, includes support for legacy USB speeds
