AMD’s next-gen Radeon RX 7000 graphics cards are slated to launch in the second half of the year with improved ray-tracing capabilities and significantly higher shader counts. Much of this will be achieved using an MCM or chiplet-based design paired with TSMC’s cutting edge 5nm process node. One of AMD’s Principal Engineers (Brian Walters) inadvertently gave up some of the specifications of the Navi 31, 32, and 33 dies (now removed). These dies are set to power the Radeon RX 7900 XT, 7800 XT, 7700 XT, and the 7600 XT:
As per his bio, the top-end Navi 31 die (parent die for the Radeon RX 7900 XT, 7800 XT, and the 7800) will leverage TSMC’s 5nm and 6nm nodes. This falls in line with what has been reported by @Greymon55 (on Twitter) in the past. A mockup of the MCM design can be seen below. Here, the Navi 31 and Navi 32 dies adopt a dual-chiplet design. The Radeon RX 7900 XT will pack up to a total of 15,360 shaders across 60 Work Group Processors (WGPs) paired with 16GB of GDDR6 memory across a 256-but bus. The L3 “Infinity” Cache will be increased to 256MB, 3D stacked upon the primary compute die. The GPU core will run at around 2.5GHz, same as Navi 21 which is a bit surprising if it’s fabbed on TSMC’s N5 node (might be N6 to improve supply). Overall, Navi 31 should easily be 2.2-2.5x faster than its predecessor, with the RX 7800 XT beating the RX 6800 XT by up to 50%.
Each Graphics Die (GCD) features three Shader Engines which are made up of two Shader Arrays each. In turn, each Shader Array packs five WGPs containing eight SIMD units (vs four on RDNA 2). The two dies are connected by a bridge interconnect paired with 256MB of L3 “Infinity” Cache. According to the source, the GCDs will be fabbed on TSMC’s 5nm (N5) node while the MCD will be fabbed on the older 6nm (N6) node. Each die should come with a 128-bit bus (divided into eight controllers), resulting in an overall bus width of 256-bit and the same external bandwidth of 448GB/s as the RX 6800 XT/6900XT.
AMD’s RDNA 3 graphics architecture is expected to get a major overhaul at the front-end, with redesigned Work Group Processors in place of Compute Units, or Dual Compute Units. With RDNA 1 and 2, the WGPs were the basic units for workload scheduling (from CUs on GCN/Vega), but it looks like that is going to change again with Navi 3x. Dual Compute Units are being discarded in favor of wider Work Group Processors, packing as many as 256 stream processors across eight 32-wide SIMDs. This means that the wave32 format of scheduling will be retained, but the number of overall active waves will be increased.
Navi 32 is also going to be a chiplet design with two compute dies and one MCD. It’ll power the Radeon RX 7700 XT. We’re looking at a core count of around 10,240 shaders (or 40WGP), and a bus width of 192-bit paired with 12GB of GDDR6 memory. The L3 “Infinity Cache” is most likely going to be cut down to 192MB 3D stacked atop the compute die. The GPU core will run between 2.6-2.8GHz. The Radeon RX 7700 XT should be around 1.5-2x faster than 6700 XT, with roughly the same power draw. Like Navi 31, it’ll be fabbed on TSMC’s 5nm and 6nm process nodes.
Finally, we have the Navi 33 die. It’ll have 4096 shaders (stream processors) across 16 WGPs. It’s expected to power the Radeon RX 7600 XT, making it a massive upgrade over the existing Radeon RX 6600 XT and its 2,304 shaders. What’s interesting is that this GPU core is set to solely leverage TSMC’s N6 node which is essentially a refresh of the N7 node. This makes it a possibility that the Radeon RX 7600 XT (which will be based on this die) will be a refresh as well.