Rumors regarding AMD’s next-gen RDNA 3 GPUs have been circulating like a plague well before the launch period. As such, before we begin, be sure to take this with a grain of salt. According to a post shared by 3DCenter on Twitter, the Navi 31 GPU will feature up to 8 cache dies as the bridge interconnect between the two Graphics Dies. This means that the Radeon RX 7900 XT may feature a total L3 cache of up to 400-800MB which quite frankly sounds insane. That much cache would alone cost as much as a high-end graphics card.
This cache would not only act as the last-level cache for the GPU but also as the interconnect between the two compute dies, holding copious amounts of data to reduce the latency penalty, much like the Game Cache on the Ryzen CPUs. In my opinion, that much cache memory seems highly unlikely. 256MB of L3 cache is more reasonable, or even 400-500MB if you’re planning to sell such a GPU for $1,500-$2,000, but 800 MB is very much out of the question.
Either way, it’s worth noting that the Navi 31 die has still not been taped out. Navi 33 is expected to be finalized and taped out very soon. Usually, the top-end products are the first to be finalized, followed by their lower-end derivatives. If Navi 31 is planned after Navi 33, it would certainly be a very strange move.
Older rumor: With Navi 31, each Graphics Die (GCD) features three Shader Engines which are made up of two Shader Arrays each. In turn, each Shader Array packs five WGPs containing eight SIMD units (vs four on RDNA 2). The two dies are connected by a bridge interconnect paired with 512MB of L3 “Infinity” Cache. According to the source, the GCDs will be fabbed on TSMC’s 5nm (N5) node while the MCD will be fabbed on the older 6nm (N6) node. Each die should come with a 128-bit bus (divided into eight controllers), resulting in an overall bus width of 256-bit and the same external bandwidth of 448GB/s as the RX 6800 XT/6900XT. Read more here.
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