According to the latest set of rumors from @Greymon55, AMD’s next-gen Radeon RX 7900 XT and 7800 XT will not only feature a chiplet design but also boast 3D stacked L3 cache. The higher-end Navi 31 and Navi 32 dies which will power the next generation of AMD’s high-performance gaming graphics cards are expected to feature up to 15,360 shaders. On the cache side, we’re looking at up to 384-512MB of 3D stacked L3 “Infinity Cache”.
The Navi 31 (RX 7900 XT) flagship will be based on an MCM (chiplet) design with a total of over 15 thousand cores (15,360 to be exact). It should easily be 2.2-2.5x faster than its predecessor, with the RX 7800 XT (Navi 33) beating the RX 6800 XT by 30-40%.
AMD’s RDNA 3 graphics architecture is expected to get a major overhaul at the front-end, with redesigned Work Group Processors in place of Compute Units, or Dual Compute Units. With RDNA 1 and 2, the WGPs were the basic units for workload scheduling (from CUs on GCN/Vega), but it looks like that is going to change again with Navi 3x. Dual Compute Units are being discarded in favor of wider Work Group Processors, packing as many as 256 stream processors across eight 32-wide SIMDs.
Each Graphics Die (GCD) features three Shader Engines which are made up of two Shader Arrays each. In turn, each Shader Array packs five WGPs containing eight SIMD units (vs four on RDNA 2). The two dies are connected by a bridge interconnect paired with 512MB of L3 “Infinity” Cache. According to the source, the GCDs will be fabbed on TSMC’s 5nm (N5) node while the MCD will be fabbed on the older 6nm (N6) node. Each die should come with a 128-bit bus (divided into eight controllers), resulting in an overall bus width of 256-bit and the same external bandwidth of 448GB/s as the RX 6800 XT/6900XT.