AMD’s RDNA 3 (Navi 3X) graphics cards are going to be a bit step up both in terms of performance as well as technological progress. With a launch slated for late 2022, these GPUs will leverage a chiplet architecture and feature never-before-seen core counts. That’s what will be needed to go neck-to-neck against NVIDIA’s Ada Lovelace architecture.
|Radeon RX 7700 XT||Radeon RX 7800 XT||Radeon RX 7900 XT|
|Chiplets||1 (mono)||2 GCD + MCD||2 GCD + MCD|
|Shaders||5,120 (20 WGPs)||10,240 (40 WGPs)||15,360 (60 WGPs)|
|Memory||12GB GDDR6||16GB GDDR6||32GB GDDR6|
|Infinity Cache||256MB||384 MB||512 MB|
|Release||Late 2022||Late 2022||Late 2022|
The Navi 31 (RX 7900 XT) flagship will be based on an MCM (chiplet) design with a total of over 15 thousand cores (15,360 to be exact). It should easily be 2.2-2.5x faster than its predecessor, with the RX 7800 XT (Navi 33) beating the RX 6800 XT by 30-40%.
AMD’s RDNA 3 graphics architecture is expected to get a major overhaul at the front-end, with redesigned Work Group Processors in place of Compute Units, or Dual Compute Units. With RDNA 1 and 2, the WGPs were the basic units for workload scheduling (from CUs on GCN/Vega), but it looks like that is going to change again with Navi 3x. Dual Compute Units are being discarded in favor of wider Work Group Processors, packing as many as 256 stream processors across eight 32-wide SIMDs.
Each Graphics Die (GCD) features three Shader Engines which are made up of two Shader Arrays each. In turn, each Shader Array packs five WGPs containing eight SIMD units (vs four on RDNA 2). The two dies are connected by a bridge interconnect paired with 512MB of L3 “Infinity” Cache. According to the source, the GCDs will be fabbed on TSMC’s 5nm (N5) node while the MCD will be fabbed on the older 6nm (N6) node. Each die should come with a 128-bit bus (divided into eight controllers), resulting in an overall bus width of 256-bit and the same external bandwidth of 448GB/s as the RX 6800 XT/6900XT.
In comparison, Navi 21 featured a Shader Engine packing 10 Dual Compute Units (20 Compute Units) which was in turn divided into two SIMDs per CU or four per DCU. Each CU featured its own vector and scalar units, along with a ray-accelerator, texture mapping units, registers, and cache. Scheduling was done on a WGP (DCU) basis, meaning four wave32 workgroups were assigned at a time. With Navi 3x, scheduling will become more complex as you’re taking 8 SIMDs or wave32 workgroups into account at once.
Navi 32 is also going to be a chiplet design with two compute dies and one MCD. It’ll be a cut-down version of Navi 31, and power the Radeon RX 7700 XT. We’re looking at a core count of around 10,240 shaders (or 40WGP), and a bus width of 192-bit paired with 16GB of GDDR6 memory. The L3 “Infinity Cache” is most likely going to be under 400MB, 384MB is the most probable figure.
According to the latest rumors, the Navi 33 die will pack 4096 shaders (stream processors). It’s expected to power the Radeon RX 7600 XT, making it a massive upgrade over the existing Radeon RX 6600 XT and its 2,304 shaders. We’re looking at an increase of more than 2x if you include the IPC, compute, and frequency gains. The Radeon RX 7600 XT is expected to pack 128-256 MB of Infinity Cache. Rumors indicate a monolithic design, with four 32-bit memory controllers for an overall bus width of 128-bit.