AMD’s Radeon RX 6700 XT graphics card is easily the most widely available RDNA 2 part on the market. It’d be safe to assume that the SKU has been one of the more successful “budget” GPUs on the market (lately). While the Navi 21-based Radeon RX 6900 XT, 6800 XT, and 6800 fight the GeForce RTX 30 series GPUs inch for inch (except in RT titles), their supplies have been very limited, much like their competitors.
According to @Greymon55, Navi 22 and 23 are likely going to get refreshes based on TSMA’s 6nm process node. This will be a late cycle refresh offering better supply rather than a performance boost compared to the original SKUs. The higher-end Navi 21 offerings will directly get an upgrade to Navi 31 and Navi 32.
The Navi 33 based Radeon RX 7700 XT and 7700 should arrive a few months after the RX 7900 XT and 7800 XT. It will be roughly on par with the Radeon RX 6000 flagship, offering a massive performance boost over its predecessor. Till then, AMD will keep the market satisfied with the Navi 22/23 refreshes. These will practically be the same chips with slightly higher boost clocks and aggressive pricing.
AMD’s Radeon RX 7900 XT flagship will be based on an MCM (chiplet) design with a total of over 15 thousand cores (15,360 to be exact) across 60 WGPs. It should easily be 2.2-2.5x faster than its predecessor, with the RX 7800 XT (Navi 33) beating the RX 6800 XT by 30-40%. The Radeon RX 7900 XT will leverage the Navi 31 dies, likely two of them. The Navi 31 will leverage up to 512 MB of L3 “Infinity Cache” 3D stacked on top of the Graphics Compute Die (GCD) or the interconnect bridge between the GCDs (much like Milan-X and Zen 3D).
The Navi 33 die will reportedly pack 4096 shaders (stream processors). It’s expected to power the Radeon RX 7600 XT, making it a massive upgrade over the existing Radeon RX 6600 XT and its 2,304 shaders. We’re looking at an increase of more than 2x if you include the IPC, compute, and frequency gains. The Radeon RX 7600 XT is expected to pack 128-256 MB of Infinity Cache. Rumors indicate a monolithic design, with four 32-bit memory controllers for an overall bus width of 128-bit.