AMD Next-Gen Zen 4 Ryzen 6000 Specs: L1, L2 Cache, and TLB Sizes

A few details from the Gigabyte leak seem to have gone unnoticed. These include (some of) the specifications of AMD’s next-gen Ryzen and Epyc processors. In essence, the memory subsystem of the Zen 4 core is included in the leaked files. We’re talking about the L1I, L1D, and L2 cache sizes associativity, TLBs, pages, entries, etc.

This is going to be a short one as there’s not a whole lot of data to sift through. We have the L1 and L2 cache sizes which come in at 32KB and 1MB, respectively. In comparison, Golden Cove has an L1D cache of 48KB and an L2 cache of 1.25MB. Zen 3 had the same L1, but an L2 cache of 512KB, so we’re looking at a 2x increase in the case of the latter. The L1 and L2 associativity are unchanged at 8-way set associative for both the L1 and L2 caches.

The L1I TLB has 64 4K pages, the L1D 72, and the L2 with 64 2M/4M. The L1I cache has 64 fully associative entries, the L1D 72, the L2 cache with 64, and the L3 with 72. The number of entries for the L12 TLB is pegged at 512, 3072 for the L2D, and 512 for the L2I. Finally, the associativity for the three is 4, 12, and 2, respectively. The L2D cache features 3072 entries with 12-way associativity.

The L3 cache is likely to stay unchanged, although we might see 3D stacked V-cache in addition to the normal L3 cluster. You can read more about Intel’s Golden Cove and AMD’s Zen 3 core here.

Source: Twitter (HansDeVriesNL)


Computer Engineering dropout (3 years), writer, journalist, and amateur poet. I started my first technology blog, Techquila while in college to address my hardware passion. Although largely successful, it was a classic example of too many people trying out multiple different things but getting nothing done. Left in late 2019 and been working on Hardware Times ever since.
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