CPUsNews

AMD Milan-X w/ 3D Stacked V-Cache to Feature 768 MB of L3 Cache and a TDP of 280W

The specifications of AMD’s upcoming Milan-X server processors have surfaced. Milan-X will be the first lineup to feature 3D stacked cache (V-Cache) in the server and data center space. Intel’s Lakefield processors were the first to demonstrate the technology in the form of Foveros, but they were very limited in scope, die area, and availability. Milan-X will retain the Zen 3 core and the N7 process from TSMC, and as such, can be thought of as a special refresh or niche stack, much like the upcoming Sapphire Rapids-SP with on-die HBM memory.

According to the source (@ExecuFix), Milan-X will consist of four SKUs ranging from 16 core all the way to 64 core. Interestingly, all of them will feature 768MB of L3 cache which is just insane, and rather excessive for the lower-end SKUs. It’s possible that the final retail parts will disable part of the L3 cache on the lower-end, but the source hasn’t indicated anything of the sort.

CPU NameCores/ThreadsBase ClockBoost ClockL3 Cache (V-Cache + L3 Cache)L2 CacheTDP
AMD EPYC 7773X64/1282.2 GHz3.5 GHz512 + 256 MB32 MB280W
AMD EPYC 7573X32/642.8 GHz3.6 GHz512 + 256 MB32 MB280W
AMD EPYC 7473X24/482.8 GHz3.7 GHz512 + 256 MB12 MB240W
AMD EPYC 7373X16/323.05 GHz3.8 GHz512 + 256 MB8 MB240W

Looking at the specs, everything’s basically identical to the vanilla Milan parts, including the base and boost clocks, the TDP as well as the L2 cache (other than the crapton of L3 cache). This means that performance gains (as already indicated earlier) will vary from application to application, and won’t be much pronounced in every workload.

Areej

Computer hardware enthusiast, engineering dropout, and PC gamer. Former co-founder of Techquila (2017-2019), a fairly successful tech outlet. Been working on Hardware Times since 2019, an outlet dedicated to computer hardware and its applications.

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