AMD Epyc Next-Gen Server CPU Layout Surfaces w/ 3rd Gen Infinity Fabric Link Architecture

AMD today unveiled its efficiency goal for its upcoming HPC and AI architectures, promising a staggering 30x increase in energy efficiency for future processors and accelerators. It’s worth noting that while these advances are aimed at the HPC and AI segments, we’ll see much of them in the server and possibly even the client space as well. AMD demoed the custom Trento Epyc processor, paired with four Instinct MI200 accelerators each, allowing for coherent memory access and simpler programming. 

Via: aschilling

As you can see, each Epyc CPU (with 64 cores) is paired with four Instinct MI200 GPUs via a 3rd Generation implementation of the Infinity Fabric (green). The four GPU accelerators, in turn, are connected to one another using the Infinity Fabric Link (in purple). Each GPU has a PCIe x16 bus for connectivity, while the CPUs are paired with octa-channel DDR5 memory and a four-lane PCIe channel.

AMD’s primary advances in power efficiency come through advanced packaging technologies including chiplets, 3D chiplets, and the Infinity Fabric architecture. Application-specific optimization of processors further fine-tunes the performance-per-watt metric.

Combining all these technologies and more, AMD is promising an efficiency gain of 30x by 2025 across its HPC and AI products including processors and accelerators.


Computer hardware enthusiast, PC gamer, and almost an engineer. Former co-founder of Techquila (2017-2019), a fairly successful tech outlet. Been working on Hardware Times since 2019, an outlet dedicated to computer hardware and its applications.

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