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AMD Epyc Milan Specs Surface: Up to 64C/128T, 32C/64T w/ 256MB L3 Cache and 4GHz Boost

According to specifications unearthed by a popular data-miner on Twitter, AMD’s Zen 3 based Epyc Milan CPUs will feature a boost clock as high as 4GHz for the 32-core part. Of course, this is the single-threaded boost clock and the all-core boost is going to be a fair bit slower, but it should allow Milan to level with Intel’s upcoming 10nm-based Ice Lake-SP which feature a sizable IPS boost over the older Skylake-class Xeon lineups.

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Compared to Rome, the core and thread counts, as well as the TDP are unchanged at 64, 128, and 280W, respectively. The total L3 cache size is also the same with an upper limit of 256MB, but the use of 8-core CCXs means that the inter-core latency is going to be significantly improved. With each core having access to twice as much L3 cache, the performance with bandwidth-intensive data center workloads should also see a notable uplift.

The highlight is the 32-core (64-thread) part which features the whole 256MB L3 stash and a TDP of 280W, the highest in the stack. It features a base clock of 2.95GHz and a boost of 4GHz. It’s likely that this chip is aimed at the upcoming 24-28 core Xeon Ice Lake-SPs which tend to the most popular. A 15% IPC uplift, higher boost clocks, and improved per-core bandwidth paired with competitive pricing should give the 3rd Gen Xeon Scalable chips a run for their money.

Areej

Computer Engineering dropout (3 years), writer, journalist, and amateur poet. I started my first technology blog, Techquila while in college to address my hardware passion. Although largely successful, it was a classic example of too many people trying out multiple different things but getting nothing done. Left in late 2019 and been working on Hardware Times ever since.
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