AMD’s Robert Hallock has confirmed that the desktop Renoir APUs don’t feature a reduced PCIe lane count. All the 7nm APUs feature a total of 24 PCIe lanes: x4 for chipset, x4 General Purpose lanes, and the remaining x16 for a discrete graphics card.
Earlier, there had been several claims that Renoir would be limited to x8 lanes similar to the mobile platform, but it seems that isn’t quite correct. The last-gen Picasso chips, namely the Ryzen 3 3200G and 3400G were also limited to 8 PCIe 3.0 lanes, but it seems like AMD has stepped up its APU game this generation by doubling the lane count.
Furthermore, all the Renoir chips will be soldered rather than feature TIM (Thermal Interface Material). Solder is more efficient at conducting heat than TIM, resulting in better temperatures. For last-gen, only the 3400G used solder. The 3200G and the low-power GE variants all used TIM.
In case you’re not sure about the difference between TIM and solder. The former is similar to thermal paste while the latter is well, solder. As already mentioned, solder is much more efficient at conducting heat but is pricier to implement.