- One of the main motivations behind the new launch is VMware's new licensing model. As per the new scheme, the pricing for processors with more than 32 cores is effectively twice as much.
AMD today announced the release of three new Epyc Rome CPUs, targeting Intel’s ST lead in the server space. The new chips feature increased operating frequency and double the amount of L3 cache compared to the existing Rome processors. AMD promises the following performance advantages over the competing Intel Xeon chips with the EPYC 7Fx2 processors:
- Up to 17% higher SQL Server performance
- Up to 47% higher VMmark 3.1 score (a new world record)
- Up to 94% higher per core computational fluid dynamics, individual application performance (HPC)
|CPU||Cores/Threads||TDP||Base/Boost||L3 Cache||Per Core L3||Price|
|7F32||8/16||180W||3.7 GHz/~3.9 GHz||128MB||16MB||$2,100|
|7F52||16/32||240W||3.5 GHz/~3.9 GHz||256MB||16MB||$3,100|
|7F72||24/48||240W||3.2 GHz/~3.7 GHz||192MB||8MB||$2,450|
The core difference between the existing Rome parts and the newer ones is with respect to the cache configuration. Like the Matisse parts, they leverage the chiplet design with the CCXs forming the basic building blocks, each with four cores and a chunk of L3 cache. The cores in a CCX can only access the L3 cache associated with that CCX, usually 16MB.
With the newer 7F32/7F52 Epyc Rome CPUs, you’ve got only one core enabled per CCX resulting in a per-core L3 cache of 16MB and two cores per CCX for the 7F72 (8MB/core). This increase in per-core cache improves the inter-core latencies and in turn single-threaded performance as well.
|CPU||Cores/Threads||Base Clock||Boost||L3 Cache||TDP||Price|
|EPYC 7702P||64 / 128||2.00||3.35||256 MB||200 W||$4,425|
|EPYC 7502P||32 / 64||2.50||3.35||128 MB||200 W||$2,300|
|EPYC 7402P||24 / 48||2.80||3.35||128 MB||200 W||$1,250|
|EPYC 7302P||16 / 32||3.00||3.30||128 MB||155 W*||$825|
|EPYC 7232P||8 / 16||3.10||3.20||32 MB||120 W||$450|
However, at the same time, the prices and TDPs have been hiked as well, making them the most power-hungry Epyc processors on the market. Even the (single-socket) 64-core 7702P draws 40W less than the newer 7F52 (16 cores). This can again be explained on the basis of the chiplet design.
The newer Rome parts feature the same number of CCDs and L3 cache as higher-end variants (with some cores disabled per CCX), and the increased frequencies further add to the higher power draw. For example, the 7F52 includes 256MB of L3 cache, the same as the 64 core 7702P. The reason being that both use the same number of CCDs, with all the cache stashes enabled. The only difference is that the latter has all the cores enabled per CCX while the former has only one.
AMD justifies this by saying that it won’t be a significant jump from its current offerings and shouldn’t be a major concern for its customers. As per Team Red, the newer chips reduce total operating costs for the target markets by as much as 50%, thereby offsetting the higher MSRP.