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AMD Big Navi Specs Leak: 80 CUs, 256-bit Bus, RX 5700 XT Successor w/ 40 CUs and 192-bit Bus (Navy Flounder)

As per the latest info found in the Linux kernel, the next-gen Navi 2x graphics cards will indeed feature up to 80 CUs paired with a 256-bit and possibly 8-16GB of GDDR6 memory. As you can see, the flagship (Big Navi) will pack two Shader Engines with each array featuring ten Dual Compute Units. That means a total of 40 DCUs or 80 CUs or 5,120 cores, twice as much as the RX 5700 XT.

ParameterNavi 10Navi 14Navi 12Sienna CichlidNavy Flounder
gc_num_se21242
gc_num_cu_per_sh1012101010
gc_num_sh_per_se22222
gc_num_rb_per_se88844
gc_num_tccs168161612
gc_num_gprs10241024102410241024
gc_num_max_gs_thds3232323232
gc_gs_table_depth3232323232
gc_gsprim_buff_depth17921792179217921792
gc_double_offchip_lds_buffer1024512102410241024
gc_wave_size3232323232
gc_max_waves_per_simd2020201616
gc_lds_size6464646464
num_sc_per_sh11111
num_packer_per_sc22244

If AMD’s memory configuration is unchanged, we’ll see two L2 blocks per 32-bit memory controller, meaning 16 for a 256-bit bus which is what Navi 21 supposedly features. The number of waves per SIMD has been reduced from 20 to 16, meaning each SIMD will hold fewer waves at a time, giving each wave higher register space or simply fewer registers. The number of vGPRs is unchanged at 1,024 and the render backends have been reduced from eight to four. This is in stark contrast to the RTX 3080 which has gotten an increased ROP count.

We also have the specifications of the RTX 5700 XT successor (Navy Flounders). This GPU will supposedly feature the same DCU and shader count as the 5700 XT, but at the same time reduce the bus size from 256-bit to 192-bit (if we go by the L2 tiles). If the RDNA 2 GPUs feature an improved IPC in the range of 15-20%, then this just might work. Otherwise, you’re basically getting the same GPUs with hardware RT units.

Furthermore, considering the reduction in the L2 cache size, it means AMD has either de-coupled the L2 cache and the memory controllers or that the company is really confident about the memory sub-structure and the cache hierarchy of its RDNA 2 GPUs:

Areej

Computer Engineering dropout (3 years), writer, journalist, and amateur poet. I started Techquila while in college to address my hardware passion. Although largely successful, it suffered from many internal weaknesses. Left and now working on Hardware Times, a site purely dedicated to. Processor architectures and in-depth benchmarks. That's what we do here at Hardware Times!
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