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A Look at Intel’s Golden Cove Core Architecture Through Sapphire Rapids-SP Die Shot: 2MB L2 and AMX Units

Some early die shots of Intel’s upcoming Sapphire Rapids-SP have revealed the Golden Cove core architecture which will be leveraged in the company’s next-gen processor lineups. Looking at the core, it appears to be roughly similar to Sunny Cove and Skylake, with one FP512 execution unit (for AVX512) and two FP256 units, and roughly the same number of registers as the former.

Golden Cove

The L2 cache has grown significantly, growing from just 512KB (per core) in Sunny Cove to an estimated 2MB in Golden Cove. The L1I cache also seems to have grown to 48KB in the latter from 32KB in the former. The most notable addition is the inclusion of AMX (matrix units) in Golden Cove which should help improve advanced Tensor instructions and therefore, accelerate neural network training.

Thanks to Locuza for the annotations

The rest of the die shots don’t reveal much about the SKU. Support for on-die HBM2 has already been a known fact for a while now, as well as the fact that SPR will feature a chiplet design with up to four tiles and a total core count of 56-60. One little tidbit is new. It looks like the 4th Gen Xeon Scalable processors will also feature an Altera FPGA, but it isn’t clear just what its function will be.

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Areej

Computer Engineering dropout (3 years), writer, journalist, and amateur poet. I started my first technology blog, Techquila while in college to address my hardware passion. Although largely successful, it was a classic example of too many people trying out multiple different things but getting nothing done. Left in late 2019 and been working on Hardware Times ever since.

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