AMD will be launching its next-gen Ryzen family featuring the Zen 4 core architecture and TSMC’s 5nm EUV process node at this time next year. This info was shared by @Greymon55 on Twitter and falls in line with what AMD has stated in the past. Along with the Ryzen 6000 processors, the chipmaker will also launch the 4th Gen Epyc Genoa and Bergamo server chips in the last quarter of 2022 and early 2023, respectively.
Both Genoa and Bergamo will be based on TSMC’s N5 (5nm EUV) node. According to AMD, Genoa will offer 2x the efficiency and 25% more performance than the existing Epyc Milan chips. In addition to a new socket (SP5), we’re looking at DDR5 memory support, PCIe Gen 5 plus CXL 1.1 integration as well. Genoa will feature as many as 128 PCIe Gen 5 lanes in a 1S and 160 in a 2S configuration. The TDP will reportedly be increased to 320W with a cTDP of up to 400W.
Bergamo, on the other hand, will be a dedicated lineup for cloud providers. Although it’ll leverage the same ISA (and socket) as Zen 4, the core complexes will be tweaked (most notably the cache) to pack sixteen cores in one CCD (vs eight on Genoa). Bergamo will feature up to 128 cores and is clearly a jab at the emergence of Arm-based designs in the cloud sector (such as those from Amazon and Google).
Coming to the client-side, Ryzen 6000 should increase the core counts across the board. We should see at least 18-20 cores on the Ryzen 9 SKUs, and 12 on the Ryzen 7. Ryzen 5 may or may not get bumped up to 8. The cache and memory subsystem of the Zen 4 family is as follows:
We have the L1 and L2 cache sizes which come in at 32KB and 1MB, respectively. In comparison, Golden Cove has an L1D cache of 48KB and an L2 cache of 1.25MB. Zen 3 had the same L1, but an L2 cache of 512KB, so we’re looking at a 2x increase in the case of the latter. The L1 and L2 associativity are unchanged at 8-way set associative for both the L1 and L2 caches.
The L1I TLB has 64 4K pages, the L1D 72, and the L2 with 64 2M/4M. The L1I cache has 64 fully associative entries, the L1D 72, the L2 cache with 64, and the L3 with 72. The number of entries for the L12 TLB is pegged at 512, 3072 for the L2D, and 512 for the L2I. Finally, the associativity for the three is 4, 12, and 2, respectively. The L2D cache features 3072 entries with 12-way associativity.
The L3 cache is likely to stay unchanged, although we might see 3D stacked V-cache in addition to the normal L3 cluster. You can read more about Intel’s Golden Cove and AMD’s Zen 3 core here. The AM5 platform will be equipped with DDR5 and PCIe Gen 5, and AM4 coolers will be compatible with the socket.
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