A sixteen core Alder Lake-S desktop CPU was today spotted in the Geekbench 5 database, indicating that Intel’s 1st 10nm desktop lineup is undergoing internal testing and verification as planned. While the scores are quite low on account of the low operating costs, we do get some other info from this listing.
For starters, the L1 and L2 cache hierarchy for the “Big” Golden Cove cores is the same as Willow Cove, with the former featuring 32KB (I)/48KB(D) and 1.25MB per core for the former and latter, respectively. The “Small” Gracemont cores will then pack 320KB of L2 cache per core and roughly the same amount of L1 cache.
When it comes to the L3 cache, we can see a massive 30 MB buffer which will be shared between the small and big cores. It’s unclear how the latency and cache bandwidth will be affected by this configuration, but considering the L3 cache size, it’s likely that it’ll be worse than existing monolithic Intel designs. As with Lakefield, the small-to-big core latency will likely be much higher than small-to-small or big-to-big core latencies. It’ll also be interesting to see what kind of bus configuration is used with these processors as it’ll play an important role in determining the inter-core latency/timings.
Intel’s Alder Lake-S CPUs based on the 10nm node are slated to launch in early 2022 with the new LGA1700 socket and possibly support for DDR5 and PCIe 4 standards.