Intel is working on 3D stacked processors and will soon have retail products based on this technology. Speaking to Tom’s Hardware, company CEO Pat Gelsinger explained that Team Blue will implement something rivaling AMD’s 3D V-Cache in future CPUs. Intel plans to leverage disaggregated cache dies in future processors, including 15th Gen Arrow Lake-S and potentially 16th Gen Lunar Lake as well. However, the implementation and use of the SRAM will vary.
In the past, we’ve seen several leaks quoting an L4 cache codenamed Adamantine or ADM. Unlike AMD’s V-Cache dies, the Adamantine or L4 cache die will sit directly below the CPU tile atop the interposer. This L4 cache will be used for various latency optimizations, caching data from the CPU, iGPU, and perhaps even the PCH. In addition to CPU gaming, this would also improve boot times, iGPU performance, and I/O latency.
According to Pat, Adamantine or L4 cache isn’t part of Meteor Lake but will be featured in future products. The CPU tile will be stacked atop the cache die using Foveros 3D stacking and EMIB interconnect. Intel will also offer this kind of 3D stacking and packaging technologies to its Foundry (IFS) customers, giving fabless chipmakers an alternative to TSMC’s CoWoS.